1. Field of the Invention
The present invention relates to semiconductor memories, and more specifically to dual-ported memories including a memory array capable of being accessed randomly and a serial access register capable of serial data transfer to and from the memory. The dual-ported two-dimensional memory of this type is commonly referred to as a video RAM.
2. Background of the Invention
The dual-ported memorv of the type discussed in this application is used, for example, for storing picture data to be input to a cathode ray tube. The picture data is randomly accessed to write or update the image in memory and then subsequently accessed serially to generate the image on a cathode ray tube. A memory of this type can store images captured by a video camera or other scanning device or it may be used to store images generated by a graphics system.
The image to be displayed is divided into a number of discrete picture elements or pixels. Each pixel represents a physical position on the output display monitor and can have associated with it a color or specific shade of gray. In image and graphics svstems the pixels of a displav are each represented bv a value stored in memorv device. This memory representation of a displav is tvpicallv referred to as a frame buffer. A high resolution displav, such as the IBM 5080 Graphics System, typically has an image of 1024.times.1024 or 1,048,576 pixels. Each pixel value can be represented by 1 to 24 or more bits thus requiring a large amount of memorv to store the image. This requirement for large amounts of high speed memory (even by modern standards) leads to the use of the highest density memory parts available for graphic system devices. Typically, Dynamic Random Access Memories ("DRAMs") provide the highest memory density. The nature of video display scan patterns and update rates pointed to a need for even faster access times and a need to decouple the updating of the frame buffer from the scanning out of the stored values (throuoh video generation circuitry) for display on the video monitor.
Video RAMs are a specialized form of Dvnamic RAM memories They were designed to solve the problem of simultaneously displaying the contents of a graphics frame buffer to the screen while allowing the graphics or image processor to update the frame buffer with new data. Video RAMs contain two Input/Output ports (one for random access and one for serial access) and one address port. These memories are frequently referred to as dual-port memories. In addition to the standard DRAM random access array of rows and columns, a Serial Access Memory register has been added to support serial input and output.
Video RAMs of this type are known in the prior art, for example U.S. Pat. No. 4,541,075 to Dill et al. describes such a memorv device. The graphics or image processor updates the frame buffer by writing into the random access arrav. The serial access memory (SAM) register is designed to sequentially shift the contents of its buffer to the displav independently of the random access array. The only time the random array and the SAM do not operate independentlv is when the SAM needs to be loaded with new data from the random array. The SAM is loaded by executing a special memory cycle called a Read Data Transfer which copies an entire row of the data to be sequentially clocked out of the SAM into circuitry which updates the screen. The clock rate of the SAM is typically between 3-4 times faster than a standard random access cvcle.
Second generation VRAMs were enhanced with the ability to transfer half a row of random access memory into half of the SAM while the other half of the SAM is being scanned out to the display. This is known as a split row transfer. An output status pin known as QSF is typicallv provided to indicate the half of the SAM being scanned out.
In some svstems there are two frame buffers, with one being scanned out to the screen while the other is being updated by the graphics or image processor. The use of two buffers avoids the problem of scanning a partiallv updated image to the screen resulting in undesirable partial images. This is frequently referred to as a double buffered system. In double buffered systems the two Frame Buffers are referred to as Frame Buffer A, FBA, and Frame Buffer B, FBB. One application of graphics displays is to segment the screen into a plurality of windows which are independent portions of the screen that each displav data from a separate application or other subset of data. Because each window is independent of the others, the current update buffer and the display buffer mav differ for different windows. Thus, at a moment on time, one window can be using Frame Buffer A for update and Frame Buffer B for displav while another window can be using the reverse. This leads to the requirement that the scan out buffer be selectable on a per pixel basis.
A graphics system that does not emplov windowing, mav have a single full screen display 90 as shown in FIG. 1A. One frame buffer, for example frame buffer B will be displaved while a second one, frame buffer A is being updated. In a certain point in time the designation of the buffers will be swapped so that the frame buffer A is being displayed while frame buffer B is being updated.
FIG. 1B illustrates the use of a windowed system. Full screen 90' may be made up of several windows such as those labeled 92, 94 and 96. Each application will maintain an indication of which frame buffer is being used for update and which is being used for display. Initiallv window 1 mav be updating frame buffer A, window 2 frame buffer B, and window 3 frame buffer A. The initial display would be window 1 from frame buffer B, window 2 from frame buffer A, and window 3 from frame buffer B. Upon the swapping of window 3 between frame buffers, updates from window 1 would be into frame buffer A, window 2 frame buffer B, and window frame buffer B, while the display will be from buffers B, A, and A respectively. While the purpose of double buffered systems is to have a separate update buffer from the display buffer, the flexibility exists to update and display from the same buffer.
One method of implementing double buffered svstems is to put the two frame buffers in separate VRAMs. With separate VRAMs it is relatively easy to synchronize the two SAM registers and select pixel data from one or the other part on a per pixel basis. This can be done, for example, by using the Serial Output Enable control pin to onlv enable the data from the desired frame buffer.
Two potential problems exist with putting the two frame buffers in separate VRAMs. First, for low resolution screens one large VRAM, e.g. 4 Mbit, could hold both frame buffers. Two VRAMs for separate frame buffers would double the frame buffer parts cost. Second, for high performance svstems, the drawing rate to the frame buffer can be increased by writing multiple pixels in parallel. If the frame buffers are separate only half of the available VRAMs can te updated in parallel. For example three 4 Mbit VRAMs are required to represent a 1280.times.1024 pixel frame buffer. Two frame buffers would require 6 VRAMs. As separate frame L buffers only the 3 VRAMs of frame buffer A or frame buffer B could be updated. If portions of each frame buffers resided in each module, then all 6 VRAMs could be updated in parallel, effectively doubling the drawing rate.
The problem solved by the present invention arises from a need to selectively scan out from FBA or FBB on a per pixel basis when both frame buffers reside in the same VRAM. The organization of the SAM in prior art devices does not provide a means to select data from FBA or FBB on a per pixel basis. The selection must be done externallv requiring a higher data rate and extra circuitry.